FIG. 1 illustrates a semiconductor device 1 that includes a semiconductor substrate 10 within which an active region 20 (schematically shown in dotted lines) is formed. The active region generally includes active and passive electronic components, such as transistors, resistors, capacitors, and the like. A first level interconnect structure includes one or more dielectric layers 11 formed above the semiconductor substrate, and conductive lines (metal tracks) 21 are formed within the dielectric layer(s) to interconnect components of the active region. The top dielectric layer 12 of the first level interconnect structure includes conductive features 22, commonly known as “chip pads”, and may be aluminum or “alucap”.
A second level interconnect structure, known as a “redistribution layer”, includes dielectric layers 13, 14 formed above layer 12, and respectively including conductive vias 23 and conductive lines 24, widening at their ends to form top pads 25. The conductive lines 24 are to redistribute electrical signals between the chip pads 22 and the pads 25, commonly arranged in a matrix on the semiconductor device. The dielectric layer 14 includes an opening 15 exposing the pad 25, such that an electrical coupling may be made between the pad and the exterior by, for example, solder balls.
During testing, packaging, and use, the pads 25 may be subjected to mechanical forces, such as test probes, pressure bonding, as well as thermo-mechanical stresses, for example when soldering the device to a package. In particular, the various materials employed in the fabrication of the semiconductor device, such as the pads and dielectric layers, have different mechanical properties and coefficients of thermal expansion. As a result, cracks may be likely to appear at the interfaces between the materials under most stress, in particular at the edges of pads 25. As shown, a crack 30 may appear at an edge 25′ of the pad 25, and propagate down through the body of the semiconductor device, and may damage underlying conductive lines 21 or enter the active region 20, which may result in a defect or failure of the device such as an open or shorted connection.
As technology progresses, the size of the features 11, 21 of the first interconnect structure diminishes, and new materials with relatively poor mechanical properties are introduced, making the interconnect structure more sensitive to cracks and other defects. In contrast, the size of the pads 25 remains substantially constant such that the pads 25 become more massive with respect to the underlying structures, which may result in an increased stress between the pads and the underlying structures and a higher likelihood of crack formation. It may therefore be desirable to provide a semiconductor device that is more protected against such cracks.